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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112773] [14 Regression] RISC-V ICE: in
 force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b
Date: Fri, 01 Dec 2023 02:01:42 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112773

--- Comment #4 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
After reproducing the ICE.

I confirm the root cause is because we enable vec_extract for mask:

;; -------------------------------------------------------------------------
;; This extracts a bit (via QImode) from a bitmask vector.
;; -------------------------------------------------------------------------
(define_expand "vec_extract<mode>qi"
  [(set (match_operand:QI         0 "register_operand")
     (vec_select:QI
       (match_operand:VB          1 "register_operand")
       (parallel
         [(match_operand          2 "nonmemory_operand")])))]


The ICE happens optimized IR is as follows:

_68 =3D BIT_FIELD_REF <mask__25.17_66, 1, POLY_INT_CST [3, 4]>;

can_align_p return false for POLY_INT_CST [3, 4] since the alignment require
multipe of 8:

force_align_down_and_div (X, BITS_PER_UNIT) -> BITS_PER_UNIT =3D 8.


It's ovbious POLY_INT_CST [3, 4] is definitely not aligned with 8.


I have no idea how to fix it.

CCing Robin who enable mask bit extraction should know much better than me.

And CCing Richard B and Richard S may give us some useful suggestions.

Thanks.=