[Bug target/112801] [14] RISC-V vector: failure to mask top bits during type conversion

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112801

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:1461b431da51f80c90c3bea03d587d76e3e50843

commit r14-6069-g1461b431da51f80c90c3bea03d587d76e3e50843
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Fri Dec 1 20:31:50 2023 +0800

    RISC-V: Fix incorrect combine of extended scalar pattern

    Background:
    RVV ISA vx instructions for example vadd.vx,
    When EEW = 64 and RV32. We can't directly use vadd.vx.
    Instead, we need to use:

    sw
    sw
    vlse
    vadd.vv

    However, we have some special situation that we still can directly use
    vadd.vx directly for EEW=64 && RV32.

    that is, when scalar is a known CONST_INT value that doesn't overflow
32-bit value.
    So, we have a dedicated pattern for such situation:

    ...
    (sign_extend:<VEL> (match_operand:<VSUBEL> 3 "register_operand"          "
r,  r,  r,  r")).
    ...

    We first force_reg such CONST_INT (within 32bit value) into a SImode reg.
    Then use such special patterns.
    Those pattern with this operand match should only value on! TARGET_64BIT.

    The PR112801 combine into such patterns on RV64 incorrectly (Those patterns
should be only value on RV32).

    This is the bug:

            andi    a2,a2,2
            vsetivli        zero,2,e64,m1,ta,ma
            sext.w  a3,a4
            vmv.v.x v1,a2
            vslide1down.vx  v1,v1,a4    -> it should be a3 instead of a4.

    Such incorrect codegen is caused by
    ...
                    (sign_extend:DI (subreg:SI (reg:DI 135 [ f.0_3 ]) 0))
                ] UNSPEC_VSLIDE1DOWN)) 16935 {*pred_slide1downv2di_extended}
    ...

    Incorretly combine into the patterns should not be valid on RV64 system.

    So add !TARGET_64BIT to all same type patterns which can fix such issue as
well as robostify the vector.md.

            PR target/112801

    gcc/ChangeLog:

            * config/riscv/vector.md: Add !TARGET_64BIT.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr112801.c: New test.