From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 0C3FC3858C54; Fri, 1 Dec 2023 02:41:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0C3FC3858C54 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1701398514; bh=3ASeL4tX+mvaEb/SRZlM9C2yCA+iPSDbPZt2NFOcrPc=; h=From:To:Subject:Date:From; b=wsLeS4ukyojxvBIO3aW5/yztm9FdsMoALGxr80g8oMx37EyfwhVtDlKXZBoopaSgu 48opQhR6pyUBYxDInu+1bV/MunhSEMtFVJq+pWKsOR8MegUTwouh2QBMtnRjFNE4Kq BOKb5dAaEKbMjSJscHdlpMe4ZE47t0/m1sRW173I= From: "patrick at rivosinc dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112801] New: [14] RISC-V vector: failure to mask top bits during type conversion Date: Fri, 01 Dec 2023 02:41:53 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: patrick at rivosinc dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112801 Bug ID: 112801 Summary: [14] RISC-V vector: failure to mask top bits during type conversion Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: patrick at rivosinc dot com Target Milestone: --- This testcase is correctly handled on rv64gc but fails on rv64gcv -O2 > ./bin/riscv64-unknown-linux-gnu-gcc -march=3Drv64gcv -mabi=3Dlp64d -O2 re= d.c -o rv64gcv.out Creduced testcase: int printf(char *, ...); int a; void c(int b) { a =3D b; } char d; char *const e =3D &d; long f =3D 66483309998; unsigned long g[2]; short h; int k; void l() { int i =3D 0; for (; i < 2; i++) { { unsigned long *m =3D &g[0]; *m &=3D 2; if (f && *e) for (;;) ; } k =3D f; g[1] =3D k; for (; h;) ; } } int main() { l(); c(g[1] >> 32); printf("%X\n", a); } Here's my analysis: Focusing on the stack of operations that lead to a: long f =3D 66483309998; // hex: F7AB6CDAE int k =3D f; // Should mask off the top bits: 7AB6CDAE unsigned long g[1] =3D k; // 7AB6CDAE int arg to c() =3D g[1]; >> 32 // 0 int a =3D arg; // 0 print(a); // 0 0 is expected but rv64gcv fails to mask the top bits and ends up printing F Tested using qemu with these commands: > ./bin/riscv64-unknown-linux-gnu-gcc -march=3Drv64gcv -mabi=3Dlp64d -O2 re= d.c -o rv64gcv.out > ./bin/riscv64-unknown-linux-gnu-gcc -march=3Drv64gc -mabi=3Dlp64d -O2 red= .c -o rv64gc.out > QEMU_CPU=3D"rv64,vlen=3D128,v=3Dtrue,vext_spec=3Dv1.0,Zve32f=3Dtrue,Zve64= f=3Dtrue" ./bin/qemu-riscv64 rv64gc.out 0 > QEMU_CPU=3D"rv64,vlen=3D128,v=3Dtrue,vext_spec=3Dv1.0,Zve32f=3Dtrue,Zve64= f=3Dtrue" ./bin/qemu-riscv64 rv64gcv.out F=