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From: "vineetg at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112817] RISC-V: RVV: provide attribute
 riscv_rvv_vector_bits for VLS codegen
Date: Wed, 06 Mar 2024 18:25:05 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112817

--- Comment #15 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
(In reply to Vineet Gupta from comment #14)
> 2. implement gcc toggle -mrvv-vector-bits=3Dzvl which essentially copies =
the
> xxx from -march string

Done:

commit 0a01d1232ff0a8b094270fbf45c9fd0ea46df19f
Author: Pan Li <pan2.li@intel.com>
Date:   Fri Feb 23 15:37:28 2024 +0800

    RISC-V: Introduce gcc option mrvv-vector-bits for RVV

    This patch would like to introduce one new gcc option for RVV. To
    appoint the bits size of one RVV vector register. Valid arguments to
    '-mrvv-vector-bits=3D' are:

    * scalable
    * zvl

    The scalable will pick up the zvl*b in the march as the minimal vlen.
    For example, the minimal vlen will be 512 when march=3Drv64gcv_zvl512b
    and mrvv-vector-bits=3Dscalable.

    The zvl will pick up the zvl*b in the march as exactly vlen.
    For example, the vlen will be 1024 exactly when march=3Drv64gcv_zvl1024b
    and mrvv-vector-bits=3Dzvl.

    The internal option --param=3Driscv-autovec-preference will be replaced
    by option -mrvv-vector-bits. Aka:

    * -mrvv-vector-bits=3Dscalable indicates
--param=3Driscv-autovec-preference=3Dscalable
    * -mrvv-vector-bits=3Dzvl indicates
--param=3Driscv-autovec-preference=3Dfixed-vlmax

    You can also take -fno-tree-vectorize for
--param=3Driscv-autovec-preference=3Dnone.
    The internal option --param=3Driscv-autovec-preference is unavailable a=
fter
this
    patch.=