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From: "sjames at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Date: Mon, 04 Dec 2023 08:40:17 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112818

Sam James <sjames at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |pan2.li at intel dot com
            Summary|[14 regression] ICE when    |[14 regression] ICE when
                   |building accel-ppp (error:  |building accel-ppp (error:
                   |conversion of register to a |conversion of register to a
                   |different size in           |different size in
                   |=E2=80=98view_convert_expr=E2=80=99,        |=E2=80=98v=
iew_convert_expr=E2=80=99,
                   |verify_gimple failed)       |verify_gimple failed) since
                   |                            |r14-5068-g88aca917eb705b

--- Comment #6 from Sam James <sjames at gcc dot gnu.org> ---
$ git bisect visualize --oneline
88aca917eb70 VECT: Refine the type size restriction of call vectorizer
1a0af6e5a99c RISC-V: Allow dest operand and accumulator operand overlap of
widen reduction instruction[PR112327]
c73d2d49f9be Daily bump.
4968e4844a3c (HEAD) Minor formatting fix for newly-added file from previous
commit
2b9778c8d9d3 Add files to discourage submissions of PRs to the GitHub mirro=
r.
80b1a371008c PR target/110551: Tweak mulx register allocation using peephol=
e2.

so yeah, let's call it r14-5068-g88aca917eb705b.=