From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 5B22A385B527; Tue, 5 Dec 2023 23:30:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5B22A385B527 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1701819050; bh=uHJfi/8XvpC3rq9GfAqu4VHDXxUQNFZDSfK/FUudnnY=; h=From:To:Subject:Date:In-Reply-To:References:From; b=OAdrCDFuwMkbbPvfMMbwl2CcDFQerXtiUHWvlfsUp1AThXSTxjAkD1RAb7hXSnqLF /lnQEVW8useWLbaln6prqi7+3aXSN3++QQxL6XGNvZcqmq9cGkLIlnMldxelA+NMjc NvJkEQZfrzxfyFnGQnSfLxgNrWxraMnMwIqahd1Q= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112852] [14 Regression] RISCV ICE: vsetvl pass: in partial_subreg_p, at rtl.h:3187 on rv64gcv_zvl512b Date: Tue, 05 Dec 2023 23:30:49 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112852 --- Comment #2 from GCC Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:2e7abd09621a4401d44f4513adf126bce4b4828b commit r14-6197-g2e7abd09621a4401d44f4513adf126bce4b4828b Author: Juzhe-Zhong Date: Tue Dec 5 20:57:27 2023 +0800 RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR This patch fixes ICE mentioned on PR112851 and PR112852. Actually these ICEs happens many times in full coverage testing. The ICE happens on: bug.c:84:1: internal compiler error: in partial_subreg_p, at rtl.h:3187 84 | } | ^ 0x11a7271 partial_subreg_p(machine_mode, machine_mode) ../../../../gcc/gcc/rtl.h:3187 gcc_checking_assert (ordered_p (outer_prec, inner_prec)); outer_prec is the PRECISION of RVVM1SImode inner_prec is the PRECISION of V64SImode when it is zvl512b. outer_prec is VLA mode with size (512, 512) inner_prec is VLS mode with size (2048, 0) Their precision/size relationship is not certain. So block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTO= R, then we never reaches the situation that comparing the precision/size between VLA size and VLS size that size > coeffs[0] of VLA mode. Note this patch cause following regression: FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize=20 scan-assembler-not vset FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize=20 scan-assembler-times li\\s+[a-x0-9]+,0\\s+ret 2 FAIL: gcc.target/riscv/rvv/base/cpymem-1.c check-function-bodies f3 FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f2 FAIL: gcc.target/riscv/rvv/base/cpymem-2.c check-function-bodies f3 1. cpymem check FAIL should be fixed on the testcase since the test is fragile which should be robostified. 2. pr111751.c is Vector cost model issue, and I will fix it in the following patch. For now, we should land this patch first (highest-priority) since it is fixing ICE. PR target/112851 PR target/112852 gcc/ChangeLog: * config/riscv/riscv-v.cc (vls_mode_valid_p): Block VLSmodes according TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/consecutive-1.c: Add LMUL = =3D 8 option. * gcc.target/riscv/rvv/autovec/vls/consecutive-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-11.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-12.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-13.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-14.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-15.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-16.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-17.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f-1.c: Adapt test. * gcc.target/riscv/rvv/autovec/pr112851.c: New test. * gcc.target/riscv/rvv/autovec/pr112852.c: New test.=