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From: "vineetg at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112853] RISC-V: RVV: SPEC2017 525.x264 regression
Date: Tue, 05 Dec 2023 00:14:48 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112853

--- Comment #1 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
Currently bisecting.

The issue happens at an indexed load insn:

=3D> 0x6f656 <intrapred_16x16_normal+668>:        vluxei64.v      v2,(a3),v2

The src reg v2 is different in good vs. failing case

bad case
----------
info reg v2
     b =3D {0xc0, 0xcf, 0xb6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0xc5, 0xb6, 0x0
<repeats 21 times>}}

good case
---------
     b =3D {0xc0, 0xcf, 0xb6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0xc5, 0xb6, 0x=
0,
0x0, 0x0, 0x0, 0x0, 0xc0, 0xcf, 0xb6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0xb0,
0xb6, 0x0, 0x0, 0x0, 0x0, 0x0}}=