From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id E45C8385840B; Wed, 6 Dec 2023 10:16:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E45C8385840B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1701857785; bh=apBnUdBFaHammhI63fK9g0W8OlqPSTwBz4QEo/rxJFc=; h=From:To:Subject:Date:In-Reply-To:References:From; b=uJ0F1NKRVsAYqaRirGpSZKHToAn5X8DkgZ2+wZnDBWKOaD2jpbAGAAFXIGv2+4PVe 97vZBlkI7vCtaF5HzqJSpJnpfcmPccDuKIm9mBm0m9eTgil0TSU3QIk1obnYBxQjLV P2CxrmsemGkkTQM5EL0inC/yVuiVeHSUh9hbmHKw= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/112854] [14] RISCV ICE: expand: in store_integral_bit_field, at expmed.cc:1049 on rv32gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax Date: Wed, 06 Dec 2023 10:16:24 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: middle-end X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112854 --- Comment #4 from GCC Commits --- The master branch has been updated by Robin Dapp : https://gcc.gnu.org/g:056cce412862f8d9b56a40dfbcbc3f9fa7f92883 commit r14-6211-g056cce412862f8d9b56a40dfbcbc3f9fa7f92883 Author: Robin Dapp Date: Tue Dec 5 15:24:12 2023 +0100 RISC-V: Add vec_init expander for masks [PR112854]. PR112854 shows a problem on rv32 with zvl1024b. During the course of expand_constructor we try to overlay/subreg a 64-element mask by a scalar (Pmode) register. This works for zvl512b and its maximum of 32 elements but fails for rv32 and 64 elements. To circumvent this this patch adds a vec_init expander for vector masks by initializing a QImode vector and comparing that against 0. gcc/ChangeLog: PR target/112854 PR target/112872 * config/riscv/autovec.md (vec_initqi): New expander. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112854.c: New test. * gcc.target/riscv/rvv/autovec/pr112872.c: New test.=