[Bug middle-end/112854] New: [14] RISCV ICE: expand: in store_integral_bit_field, at expmed.cc:1049 on rv32gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[Bug middle-end/112854] New: [14] RISCV ICE: expand: in store_integral_bit_field, at expmed.cc:1049 on rv32gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112854

            Bug ID: 112854
           Summary: [14] RISCV ICE: expand: in store_integral_bit_field,
                    at expmed.cc:1049 on rv32gcv_zvl1024b
                    --param=riscv-autovec-preference=fixed-vlmax
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Created attachment 56802
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56802&action=edit
-freport-bug output

Command:
> /scratch/tc-testing/tc-dec-4-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -O3 red.c -freport-bug
during RTL pass: expand
red.c: In function 'c':
red.c:2:6: internal compiler error: in store_integral_bit_field, at
expmed.cc:1049
    2 | void c(int d) {
      |      ^
0x9b17de store_integral_bit_field
        ../../../gcc/gcc/expmed.cc:1049
0x9b17de store_bit_field_1
        ../../../gcc/gcc/expmed.cc:884
0xe4c83d store_bit_field(rtx_def*, poly_int<2u, unsigned long>, poly_int<2u,
unsigned long>, poly_int<2u, unsigned long>, poly_int<2u, unsig
        ../../../gcc/gcc/expmed.cc:1193
0xe783e8 store_field
        ../../../gcc/gcc/expr.cc:8231
0xe768ba store_constructor(tree_node*, rtx_def*, int, poly_int<2u, long>, bool)
        ../../../gcc/gcc/expr.cc:7986
0xe791e8 expand_constructor
        ../../../gcc/gcc/expr.cc:9329
0xe641f8 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
        ../../../gcc/gcc/expr.cc:11605
0xe649a9 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
        ../../../gcc/gcc/expr.cc:11220
0xf99ff2 expand_normal(tree_node*)
        ../../../gcc/gcc/expr.h:319
0xf99ff2 expand_vec_cond_mask_optab_fn
        ../../../gcc/gcc/internal-fn.cc:3116
0xf99ff2 expand_VCOND_MASK
        ../../../gcc/gcc/internal-fn.def:235
0xd2cd07 expand_call_stmt
        ../../../gcc/gcc/cfgexpand.cc:2738
0xd2cd07 expand_gimple_stmt_1
        ../../../gcc/gcc/cfgexpand.cc:3881
0xd2cd07 expand_gimple_stmt
        ../../../gcc/gcc/cfgexpand.cc:4045
0xd31ca0 expand_gimple_basic_block
        ../../../gcc/gcc/cfgexpand.cc:6101
0xd33c36 execute
        ../../../gcc/gcc/cfgexpand.cc:6836
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Preprocessed source stored into /scratch/tmp/ccZuP8B4.out file, please attach
this to your bugreport.

Reduced testcase:
short a, b;
void c(int d) {
  for (; a; a--) {
    b = 0;
    for (; b <= 8; b++)
      if (d)
        break;
  }
}

Godbolt:
https://godbolt.org/z/9YGs9jTfv

[Bug middle-end/112854] [14] RISCV ICE: expand: in store_integral_bit_field, at expmed.cc:1049 on rv32gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112854

--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
I have noticed in full coverage testing.

It's mask bit field related issue again.

Robin could you take a look at it ?

I think you are the better one than me to take care of it.

Thanks.

[Bug middle-end/112854] [14] RISCV ICE: expand: in store_integral_bit_field, at expmed.cc:1049 on rv32gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112854

--- Comment #2 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Hehe I was hoping we wouldn't hit a vec_set on a mask but apparently this
happens as well.  We don't have a pattern for that either, yet.

Thanks for the test.  I would expect this to be fixed in a similar way to the
vec_extract problem but let's see.

[Bug middle-end/112854] [14] RISCV ICE: expand: in store_integral_bit_field, at expmed.cc:1049 on rv32gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112854

--- Comment #3 from Robin Dapp <rdapp at gcc dot gnu.org> ---
The problem seems to be that we can overlay a 32-bit bitmask with an SImode
subreg and work with it.  For zvl1024b on rv32 we don't allow this causing the
ICE.

We might be able to work around it by providing a vec_init for mask modes so we
don't use the subreg code.  I wonder why the vec_duplicate expander we already
have is not sufficient, though. Need to see where things go wrong.

[Bug middle-end/112854] [14] RISCV ICE: expand: in store_integral_bit_field, at expmed.cc:1049 on rv32gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112854

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:

https://gcc.gnu.org/g:056cce412862f8d9b56a40dfbcbc3f9fa7f92883

commit r14-6211-g056cce412862f8d9b56a40dfbcbc3f9fa7f92883
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Tue Dec 5 15:24:12 2023 +0100

    RISC-V: Add vec_init expander for masks [PR112854].

    PR112854 shows a problem on rv32 with zvl1024b.  During the course of
    expand_constructor we try to overlay/subreg a 64-element mask by a
    scalar (Pmode) register.  This works for zvl512b and its maximum of
    32 elements but fails for rv32 and 64 elements.

    To circumvent this this patch adds a vec_init expander for vector masks
    by initializing a QImode vector and comparing that against 0.

    gcc/ChangeLog:

            PR target/112854
            PR target/112872

            * config/riscv/autovec.md (vec_init<mode>qi): New expander.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr112854.c: New test.
            * gcc.target/riscv/rvv/autovec/pr112872.c: New test.

[Bug middle-end/112854] [14] RISCV ICE: expand: in store_integral_bit_field, at expmed.cc:1049 on rv32gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112854

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #5 from Patrick O'Neill <patrick at rivosinc dot com> ---
Fixed. Thank you!