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From: "patrick at rivosinc dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112855] New: [14] RISC-V vector: overwriting stack args
Date: Tue, 05 Dec 2023 05:21:43 +0000	[thread overview]
Message-ID: <bug-112855-4@http.gcc.gnu.org/bugzilla/> (raw)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112855

            Bug ID: 112855
           Summary: [14] RISC-V vector: overwriting stack args
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

reduced testcase:
int printf(char *, ...);
int a;
int b = 100;
int c[25];
int d;
int main() {
  int e;
  d = 0;
  for (; d < 5; d++) {
    e = 0;
    for (; e < 5; e++)
      c[d * 5 + e] = 0;
  }
  if (b)
    if (a)
      for (;;)
        ;
  b++;
  int volatile f = *c;
  printf("%d\n", b);
}

Tested using qemu with these commands:
> ./bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d -O3 red.c -o rv64gcv.out

> ./bin/riscv64-unknown-linux-gnu-gcc -march=rv64gc -mabi=lp64d -O3 red.c -o rv64gc.out

> QEMU_CPU=rv64,vlen=128,v=true,vext_spec=v1.0,Zve32f=true,Zve64f=true ./bin/qemu-riscv64 rv64gc.out
101

> QEMU_CPU=rv64,vlen=128,v=true,vext_spec=v1.0,Zve32f=true,Zve64f=true ./bin/qemu-riscv64 rv64gcv.out
5

rv64gcv should match rv64gc and output 101. I'm not sure where it's getting "5"
from.

When you comment out the b++, the behavior is fixed (and both rv64gcv and
rv64gc output 100):
https://godbolt.org/z/chqGo6fj8

Changing other aspects of the program will also fix the behavior, it's just
that commenting out b++ was the least-disruptive change on the assembly code
that I could find.

You can also set b to zero. I just have it at 100 to make it more obvious that
the arg is getting overwritten, not just added/subtracted.

             reply	other threads:[~2023-12-05  5:21 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-05  5:21 patrick at rivosinc dot com [this message]
2023-12-05 18:54 ` [Bug target/112855] [14] RISC-V vector: vsetivli clobbers variable value patrick at rivosinc dot com
2023-12-06 14:36 ` cvs-commit at gcc dot gnu.org
2023-12-06 18:54 ` patrick at rivosinc dot com

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