[Bug target/112930] gcc.target/aarch64/sme/call_sm_switch_7.c ICEs on aarch64_be

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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112930

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Richard Sandiford <rsandifo@gcc.gnu.org>:

https://gcc.gnu.org/g:f5c8d6bc050a8a6120aff2be25b6892d91baac99

commit r14-6386-gf5c8d6bc050a8a6120aff2be25b6892d91baac99
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Sun Dec 10 19:46:06 2023 +0000

    aarch64: Fix SMSTART/SMSTOP save/restore for BE

    VNx16QI (the SVE register byte mode) is the only SVE mode for which
    LD1 and LDR result in the same register layout for big-endian.  It is
    therefore the only mode for which we allow LDR and STR to be used for
    big-endian SVE moves.

    The SME support sometimes needs to use LDR and STR to save and restore
    Z register contents around an SMSTART/SMSTOP SM.  It therefore needs
    to use VNx16QI regardless of the type of value that is stored in the
    Z registers.

    gcc/
            PR target/112930
            * config/aarch64/aarch64.cc
(aarch64_sme_mode_switch_regs::add_reg):
            Force specific SVE modes for single registers as well as
structures.