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From: "acoplan at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113062] [14 Regression][aarch64] ICE in fuse_pair, at
 config/aarch64/aarch64-ldp-fusion.cc:1456 since r14-6605-gc0911c6b357ba9
Date: Mon, 18 Dec 2023 15:36:11 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113062

--- Comment #2 from Alex Coplan <acoplan at gcc dot gnu.org> ---
So we try to combine these two insns:

(insn 14 82 16 2 (set (mem/c:TF (plus:DI (reg/f:DI 31 sp)
                (const_int 32 [0x20])) [3 %sfp+-32 S16 A128])
        (asm_operands:TF ("") ("=3Dg") 0 [
                (mem/c:TF (plus:DI (reg/f:DI 31 sp)
                        (const_int 32 [0x20])) [3 %sfp+-32 S16 A128])
            ]
             [
                (asm_input:TF ("0") t.c:5)
            ]
             [] t.c:5)) "t.c":5:6 -1
     (nil))
(insn 16 14 19 2 (set (mem/c:TF (plus:DI (reg/f:DI 31 sp)
                (const_int 48 [0x30])) [3 %sfp+-16 S16 A128])
        (asm_operands:TF ("") ("=3Dg") 0 [
                (mem/c:TF (plus:DI (reg/f:DI 31 sp)
                        (const_int 48 [0x30])) [3 %sfp+-16 S16 A128])
            ]
             [
                (asm_input:TF ("0") t.c:5)
            ]
             [] t.c:5)) "t.c":5:6 -1
     (nil))

I think we aren't expecting to see memory operands in the RHS of the stores=
, I
think the pass needs to reject invalid operands earlier before we even start
tracking them.

Testing a patch.=