From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 391C33858C54; Fri, 29 Dec 2023 08:16:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 391C33858C54 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1703837770; bh=MjUR4mIHpk8qBvDijDrc/kHoH4sjLl652Y6Gsly7bWI=; h=From:To:Subject:Date:In-Reply-To:References:From; b=qzpu7aBC8gpOgkejY26m7Cvj+K3IjT2ldR0RKvaKoK1Z51x+/FCmL/DDcC+6vg8Qz sfj8tJdIv3hSMSPyR15e103fFcp9WqjXNUnzjKwqwbcgQIaEgWxxfcHX4akggAEwJL 2hXYaoJ3jviobluaLM6jN3ej1G17lRkrUU8bINBU= From: "ubizjak at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/113133] [14 Regression] ICE: SIGSEGV in mark_label_nuses(rtx_def*) (emit-rtl.cc:3896) with -O -fno-tree-ter -mavx512f -march=barcelona Date: Fri, 29 Dec 2023 08:16:09 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: ubizjak at gmail dot com X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: ubizjak at gmail dot com X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113133 --- Comment #8 from Uro=C5=A1 Bizjak --- (In reply to Haochen Jiang from comment #6) > Aha, I see what happened. x/ymm16+ are usable for AVX512F w/o AVX512VL and > that is why I added that to allow them. >=20 > Let me find a way to see if we can fix this. It looks to me that ix86_hard_regno_mode_ok should be fixed to allow x/ymm1= 6+ also with EVEX512. Currently we have: /* TODO check for QI/HI scalars. */ /* AVX512VL allows sse regs16+ for 128/256 bit modes. */ if (TARGET_AVX512VL && (VALID_AVX256_REG_OR_OI_MODE (mode) || VALID_AVX512VL_128_REG_MODE (mode))) return true; so the compiler is unable to change some of the modes of the xmm16 to 128-b= it mode using lowpart_subreg, e.g. DFmode to V4SFmode. Please also note that your original patch missed to add TARGET_EVEX512 to t= he splitter that handles float_truncate with TARGET_USE_VECTOR_FP_CONVERTS. I propose to proceed with the minimal fix from Comment #3 as a hotfix to unbreak the testcase in this PR. The real, but more involved fix is to fix ix86_hard_regno_mode_ok, which I'll leave to you.=