From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
	id 6428D385829F; Tue, 30 Jan 2024 11:05:01 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6428D385829F
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1706612701;
	bh=xBQ8QBO3O2vwHfwAsaE4Dh2SwBgAAqoCUAbch34/whs=;
	h=From:To:Subject:Date:In-Reply-To:References:From;
	b=bV+m29szVCDsB/H9qRIwnO/g3hj9lGycqPH1+pBRU7Qw5zDZxklM4I+h+VlG4QRpa
	 xcI2ZwJRfSz280ZwvYR39qR1zof2REMOA4fM/zaIu7KtKoryEKlJ+9o1FoPwayfKq6
	 cqGO1h9hUUzjSwfqUwcemUL2X+LyOCsjaTcuQVJE=
From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/113166] RISC-V: Redundant move instructions in RVV
 intrinsic codes
Date: Tue, 30 Jan 2024 11:04:58 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: middle-end
X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: missed-optimization, ra
X-Bugzilla-Severity: normal
X-Bugzilla-Who: juzhe.zhong at rivai dot ai
X-Bugzilla-Status: UNCONFIRMED
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-113166-4-UOrXWqfyFB@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-113166-4@http.gcc.gnu.org/bugzilla/>
References: <bug-113166-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
List-Id: <gcc-bugs.sourceware.org>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113166

--- Comment #3 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
#include <cstdint>
#include <riscv_vector.h>

template <size_t length>
inline vuint8m1_t tail_load(void const* data);

template<>
inline vuint8m1_t tail_load<sizeof(uint64_t)>(void const* data) {
    uint64_t const* ptr64 =3D reinterpret_cast<uint64_t const*>(data);
#if 1
    const vuint64m1_t zero =3D __riscv_vmv_v_x_u64m1(0,
__riscv_vsetvlmax_e64m1());
    vuint64m1_t v64 =3D __riscv_vslide1up(zero, *ptr64,
__riscv_vsetvlmax_e64m1());
    return __riscv_vreinterpret_u8m1(v64);
#elif 1
    vuint64m1_t v64 =3D __riscv_vmv_s_x_u64m1(*ptr64, 1);
    const vuint64m1_t zero =3D __riscv_vmv_v_x_u64m1(0,
__riscv_vsetvlmax_e64m1());
    v64 =3D __riscv_vslideup(v64, zero, 1, __riscv_vsetvlmax_e8m1());
    return __riscv_vreinterpret_u8m1(v64);
#elif 1
    vuint64m1_t v64 =3D __riscv_vle64_v_u64m1(ptr64, 1);
    const vuint64m1_t zero =3D __riscv_vmv_v_x_u64m1(0,
__riscv_vsetvlmax_e64m1());
    v64 =3D __riscv_vslideup(v64, zero, 1, __riscv_vsetvlmax_e8m1());
    return __riscv_vreinterpret_u8m1(v64);
#else
    vuint8m1_t v =3D __riscv_vreinterpret_u8m1(__riscv_vle64_v_u64m1(ptr64,=
 1));
    const vuint8m1_t zero =3D __riscv_vmv_v_x_u8m1(0, __riscv_vsetvlmax_e8m=
1());
    return __riscv_vslideup(v, zero, sizeof(uint64_t),
__riscv_vsetvlmax_e8m1());
#endif
}

vuint8m1_t test2(uint64_t data) {
    return tail_load<sizeof(data)>(&data);
}

GCC ASM:

test2(unsigned long):
        vsetvli a5,zero,e64,m1,ta,ma
        vmv.v.i v8,0
        vmv1r.v v9,v8=20=20=20
        vslide1up.vx    v8,v9,a0
        ret

LLVM ASM:

test2(unsigned long):                              # @test2(unsigned long)
        vsetvli a1, zero, e64, m1, ta, ma
        vmv.v.i v9, 0
        vslide1up.vx    v8, v9, a0
        ret=