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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/113179] [11/12/13/14/15 Regression] MIPS: INS is
 used for long long, before SLL
Date: Mon, 06 May 2024 04:10:49 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113179

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by YunQiang Su <syq@gcc.gnu.org>:

https://gcc.gnu.org/g:7d5d2b879ae7636ca118fb4f3a08b22705cdeacb

commit r15-171-g7d5d2b879ae7636ca118fb4f3a08b22705cdeacb
Author: YunQiang Su <syq@gcc.gnu.org>
Date:   Mon Apr 29 00:33:44 2024 +0800

    expmed: TRUNCATE value1 if needed in store_bit_field_using_insv

    PR target/113179.

    In `store_bit_field_using_insv`, we just use SUBREG if value_mode
    >=3D op_mode, while in some ports, a sign_extend will be needed,
    such as MIPS64:
      If either GPR rs or GPR rt does not contain sign-extended 32-bit
      values (bits 63..31 equal), then the result of the operation is
      UNPREDICTABLE.

    The problem happens for the code like:
      struct xx {
            int a:4;
            int b:24;
            int c:3;
            int d:1;
      };

      void xx (struct xx *a, long long b) {
            a->d =3D b;
      }

    In the above code, the hard register contains `b`, may be note well
    sign-extended.

    gcc/
            PR target/113179
            * expmed.cc(store_bit_field_using_insv): TRUNCATE value1 if
            needed.

    gcc/testsuite
            PR target/113179
            * gcc.target/mips/pr113179.c: New tests.=