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From: "patrick at rivosinc dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113210] [14] RISC-V vector ICE: tree check: expected
 integer_cst, have cond_expr in get_len, at tree.h:6481
Date: Tue, 02 Jan 2024 23:48:13 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113210

--- Comment #2 from Patrick O'Neill <patrick at rivosinc dot com> ---
On 1/2/24 15:38, juzhe.zhong at rivai dot ai wrote:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113210
>
> --- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
> This is not RISC-V issues, it's middle-end issue.
> Plz change the title and CC Richard.
>
> https://godbolt.org/z/1bj9xaYTa
>
> ARM SVE has the same issue.
>
Got it - Bugzilla seems to be down for me.
Once it's back up I'll update the PR.

Thanks,
Patrick=