From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 7C14B3857C5C; Thu, 4 Jan 2024 09:22:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7C14B3857C5C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1704360162; bh=AU/lNNxeG1g1Cf6e1rVI3wl+mcbJZxjdbPfMfKCUTis=; h=From:To:Subject:Date:In-Reply-To:References:From; b=MyDUbhtWcert9fcd9+lDk+YRcBP9qgep3ViBoW8wRonWez887ZxFU5Kt5MSrwlWMr 55oY20rxllhlbGUG4b9kB9MFRLUWHKBPHz9V0VjmIW9cidQCxRhl05ZakSpJ0FFxOx 6KmbKT8ap+dyfnPeu0V23L1fVf9A8IjBPeoTrryA= From: "pinskia at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/113231] x86_64 uses SSE instructions for `*mem <<= const` at -Os Date: Thu, 04 Jan 2024 09:22:41 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: pinskia at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: short_desc cf_reconfirmed_on keywords bug_status everconfirmed Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113231 Andrew Pinski changed: What |Removed |Added ---------------------------------------------------------------------------- Summary|x86_64 use MMX instructions |x86_64 uses SSE |for simple shift operations |instructions for `*mem <<= =3D | |const` at -Os Last reconfirmed| |2024-01-04 Keywords| |missed-optimization Status|UNCONFIRMED |NEW Ever confirmed|0 |1 --- Comment #2 from Andrew Pinski --- > Registers conversion cost: 0 In this case we start off with: ``` (insn 6 3 0 2 (parallel [ (set (mem:SI (reg/v/f:DI 100 [ iD.2766 ]) [1 *i_4(D)+0 S4 A32]) (ashift:SI (mem:SI (reg/v/f:DI 100 [ iD.2766 ]) [1 *i_4(D)+= 0 S4 A32]) (const_int 1 [0x1]))) (clobber (reg:CC 17 flags)) ]) "/app/example.cpp":3:8 911 {*ashlsi3_1} (expr_list:REG_DEAD (reg/v/f:DI 100 [ iD.2766 ]) (expr_list:REG_UNUSED (reg:CC 17 flags) (nil)))) ``` Which has 0 registers usage but then STV does not take into account the need for the load/store for SSE registers.=