[Bug tree-optimization/113281] [11 Regression] Latent wrong code due to vectorization of shift reduction and missing promotions since r9-1590

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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281

--- Comment #34 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Alexandre Oliva <aoliva@gcc.gnu.org>:

https://gcc.gnu.org/g:54d2339c9f87f702e02e571a5460e11c19e1c02f

commit r15-1639-g54d2339c9f87f702e02e571a5460e11c19e1c02f
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Wed Jun 26 02:08:18 2024 -0300

    [testsuite] [arm] [vect] adjust mve-vshr test [PR113281]

    The test was too optimistic, alas.  We used to vectorize shifts by
    clamping the shift counts below the bit width of the types (e.g. at 15
    for 16-bit vector elements), but (uint16_t)32768 >> (uint16_t)16 is
    well defined (because of promotion to 32-bit int) and must yield 0,
    not 1 (as before the fix).

    Unfortunately, in the gimple model of vector units, such large shift
    counts wouldn't be well-defined, so we won't vectorize such shifts any
    more, unless we can tell they're in range or undefined.

    So the test that expected the vectorization we no longer performed
    needs to be adjusted.  Instead of nobbling the test, Richard Earnshaw
    suggested annotating the test with the expected ranges so as to enable
    the optimization, and Christophe Lyon suggested a further
    simplification.


    Co-Authored-By: Richard Earnshaw <Richard.Earnshaw@arm.com>

    for  gcc/testsuite/ChangeLog

            PR tree-optimization/113281
            * gcc.target/arm/simd/mve-vshr.c: Add expected ranges.