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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113326] Optimize vector shift with constant delta on
 shifting-count operand
Date: Thu, 11 Jan 2024 07:56:50 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113326

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Feng Xue from comment #3)
> (In reply to Andrew Pinski from comment #1)
> > Note on aarch64 with SVE, you should be able to generate those constants
> > without a load, using the index instruction.
> Ok. Thanks for the note. This still requires an extra instruction, while =
the
> constant delta could be nested in shift instruction as IMM operand.
>=20
> > Basically this requires an "un-shift" pass and most likely should be do=
ne at
> > the RTL level though that might be too late.
> > Maybe isel?
> I'm thinking of adding the processing in pass_lower_vector_ssa, which also
> contains other peephole vector ssa optimizations, not just lowering.

It should be in isel like other vector instruction selection that goes on.

pass_lower_vector_ssa is only for lowing generic vectors.=