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From: "liuhongt at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113345] miss optimization for psign{b,w,d}.
Date: Fri, 12 Jan 2024 02:30:34 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113345

--- Comment #1 from Hongtao Liu <liuhongt at gcc dot gnu.org> ---

>=20
> maybe we can just refactor the pattern as blow, then combine can generate
> the pattern for us.
>=20
> 22115(define_insn "<ssse3_avx2>_psign<mode>3"
> 22116  [(set (match_operand:VI124_AVX2 0 "register_operand" "=3Dx,x")
> 22117        (unspec:VI124_AVX2
> 22118          [(match_operand:VI124_AVX2 1 "register_operand" "0,x")
>                 (neg:VI124:(match_dup 1)
> 22119           (match_operand:VI124_AVX2 2 "vector_operand" "xja,xjm")]
> 22120          UNSPEC_PBLENDV))]

Not for VI2, but ok for VI14.=