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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113510] [14 Regression] [ARM Thumb] ICE in
 extract_constrain_insn with CPU cortex-m23
Date: Tue, 05 Mar 2024 17:35:25 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113510

--- Comment #8 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Earnshaw <rearnsha@gcc.gnu.or=
g>:

https://gcc.gnu.org/g:067a012bde15bfb62d9af309d9d524ebfe91b705

commit r14-9322-g067a012bde15bfb62d9af309d9d524ebfe91b705
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Tue Mar 5 17:21:43 2024 +0000

    arm: check for low register before applying peephole [PR113510]

    For thumb1, when using a peephole to fuse

            mov reg, #const
            add reg, reg, SP

    into

            add reg, SP, #const

    we must first check that reg is a low register, otherwise we will ICE
    when trying to recognize the resulting insn.

    gcc/ChangeLog:

            PR target/113510
            * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
            low_register_operand.=