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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113607] [14] RISC-V rv64gcv vector: Runtime mismatch at
 -O3
Date: Tue, 30 Jan 2024 22:12:31 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113607

--- Comment #20 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Robin Dapp from comment #19)
> What seems odd to me is that in fre5 we simplify
>=20
>   _429 =3D .COND_SHL (mask_patt_205.47_276, vect_cst__262, vect_cst__262,=
 { 0,
> ... });
>   vect_prephitmp_129.51_282 =3D _429;
>   vect_iftmp.55_287 =3D VEC_COND_EXPR <mask_patt_209.54_286,
> vect_prephitmp_129.51_282, vect_cst__262>;
>=20
> to
>=20
> Applying pattern match.pd:9607, gimple-match-10.cc:3817
> gimple_simplified to vect_iftmp.55_287 =3D .COND_SHL (mask_patt_205.47_27=
6,
> vect_cst__262, vect_cst__262, { 0, ... });
>=20
> so fold
>=20
> vec_cond (mask209, prephitmp129, vect_cst262)
> with prephitmp129 =3D cond_shl (mask205, vect_cst262, vect_cst262, 0)
>=20
> into
> cond_shl =3D (mask205, vect_cst262, vect_cst262, 0)?
>=20
> That doesn't look valid to me because the vec_cond's else value
> (vect_cst262) gets lost.  Wouldn't such a simplification have a condition=
al
> else value?
> Like !mask1 ? else1 : else2 instead of else2 unconditionally?

Does ARM SVE have the same issue too ? Since I think we should be using same
folding optimization as ARM SVE.=