From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id C69213858407; Wed, 31 Jan 2024 02:16:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C69213858407 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1706667386; bh=/g/SUTkN7YTzkhQ0mJ+uOy9FCcCF0o3MdfS9b/4J6BE=; h=From:To:Subject:Date:In-Reply-To:References:From; b=GiL3qJiPIsb5+PbHf7G//fEqrQTdfAN7dQmm40aRMOWTgQlXGUDEjPRS8pdEkkrWp TMKtCCBx294PqjX0+XwGAF5nhqSsG4dw2Heco8tIlXuWN/LQlCNSVRzH1k3zfjAGOD DdM1HL03IPWFjgmlJLE6ZfFLrzM4OhpuERGOxalU= From: "pinskia at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/113677] Missing `VEC_PERM_EXPR <{a, CST}, CST, {0, 1, 2, ...}>` optimization Date: Wed, 31 Jan 2024 02:16:20 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: pinskia at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cf_gcctarget Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113677 Andrew Pinski changed: What |Removed |Added ---------------------------------------------------------------------------- Target|x86_64 |x86_64 aarch64 --- Comment #2 from Andrew Pinski --- Here is another example, using 64/128 on aarch64: ``` #define vect64 __attribute__((vector_size(8) )) #define vect128 __attribute__((vector_size(16) )) vect128 unsigned int f(vect64 unsigned int a) { vect64 unsigned int zero=3D{0, 0}; return __builtin_shufflevector (a, zero, 0, 1, 2, 3); } ``` We get: ``` f: movi v31.4s, 0 fmov d0, d0 zip1 v0.2d, v0.2d, v31.2d ``` This should just produce the `fmov` for little-endian and `mov/ins` for big-endian. Note for this part of the issue the aarch64 back-end represents zip using UNSPEC where it could use VEC_CONCAT instead. And it would do the correct t= hing there ...=