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From: "mumuxi_ll at outlook dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug c/113715] New: RISC-V: If the Zcmp is enabled, the a0 register
 operates abnormally when the program returns
Date: Fri, 02 Feb 2024 08:51:44 +0000
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X-Bugzilla-Product: gcc
X-Bugzilla-Component: c
X-Bugzilla-Version: 14.0
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X-Bugzilla-Who: mumuxi_ll at outlook dot com
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113715

            Bug ID: 113715
           Summary: RISC-V: If the Zcmp is enabled, the a0 register
                    operates abnormally when the program returns
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: mumuxi_ll at outlook dot com
  Target Milestone: ---

When compiling the following test.c code with the options
-march=3Drv32ima_zca_zcb_zcmp_zcmt -mabi=3Dilp32 -Os, a bug appears when gcc
enables zcmp. In the disassembly dump.txt, it can be observed that when
executing the bne instruction in test_err, a0 is not set to 0 as the functi=
on
return value.

Source code:

void test_1(int onoff)
{
    for (volatile int i =3D 0; i < 100; i ++) {

    }
}

int test_err(void *param, int mode, int *saveAddr)
{
    if (mode =3D=3D 2) {
        test_1(1);
    }

    return 0;
}

int main()
{
    int ret =3D test_err((void *)0x123456, 3, (int *)0x123456);
    for (volatile int i =3D ret; i < 100; i ++) {
        ret =3D i * i;
    }
    return ret;
}


GCC ASM:

test_1:
        addi    sp,sp,-16
        sw      zero,12(sp)
        li      a4,99
.L2:
        lw      a5,12(sp)
        ble     a5,a4,.L3
        addi    sp,sp,16
        jr      ra
.L3:
        lw      a5,12(sp)
        addi    a5,a5,1
        sw      a5,12(sp)
        j       .L2
test_err:
        li      a5,2
        bne     a1,a5,.L8
        li      a0,1
        cm.push {ra}, -16
        call    test_1
        cm.popretz      {ra}, 16
.L8:
        ret
main:
        addi    sp,sp,-16
        sw      zero,12(sp)
        li      a0,0
        li      a3,99
.L12:
        lw      a5,12(sp)
        ble     a5,a3,.L13
        addi    sp,sp,16
        jr      ra
.L13:
        lw      a0,12(sp)
        lw      a4,12(sp)
        mul     a0,a0,a4
        lw      a4,12(sp)
        addi    a4,a4,1
        sw      a4,12(sp)
        j       .L12=