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From: "miro.kropacek at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113779] Very inefficient m68k code generated for simple
 copy loop
Date: Tue, 06 Feb 2024 12:58:30 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113779

--- Comment #5 from Miro Kropacek <miro.kropacek at gmail dot com> ---
I have been told that one of the reasons why post-incrementing modes are not
supported / preferred these days is that they halt the CPU pipeline (of cou=
rse,
totally not applicable on m68k). So with the offsets you can parallelize the
movements while when post-incrementing the values of a1, you always have to
wait for the previous instruction to finish.

So I could understand that this has been changed but it definitely shouldn'=
t be
a change involving all possible CPUs.=