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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113856] New: `(vect64 float){1.0f, 0}` code generation
 could just be `fmov sN, 1.0f`
Date: Fri, 09 Feb 2024 23:30:09 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: new
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X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: missed-optimization
X-Bugzilla-Severity: normal
X-Bugzilla-Who: pinskia at gcc dot gnu.org
X-Bugzilla-Status: UNCONFIRMED
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D113856

            Bug ID: 113856
           Summary: `(vect64 float){1.0f, 0}` code generation could just
                    be `fmov sN, 1.0f`
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pinskia at gcc dot gnu.org
  Target Milestone: ---

Take:
```
#define vect64 __attribute__((vector_size(8) ))

vect64  float f1( float a)
{
  return (vect64 float){1.0f, 0};
}
vect64  float f2( float a)
{
  return (vect64 float){1.0f, 1.0f};
}
```

Currently GCC produces:
```
f1:
        adrp    x0, .LC0
        ldr     d0, [x0, #:lo12:.LC0]
        ret
f2:
        fmov    v0.2s, 1.0e+0
        ret
```


But f1 could be implemented using fmov also.
Like:
```
f1:
        fmov    s0, 1.0e+0
        ret
```=