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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/113913] [14] RISC-V: suboptimal code gen for intrinsic vcreate
Date: Tue, 13 Feb 2024 22:54:14 +0000 [thread overview]
Message-ID: <bug-113913-4-T6fw3BpmPR@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-113913-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113913
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
Last reconfirmed| |2024-02-13
Keywords| |ra
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
This looks like a subreg issue:
```
(insn 18 17 8 2 (set (reg:RVVM2SF 134 [ <retval> ])
(if_then_else:RVVM2SF (unspec:RVVMF16BI [
(const_vector:RVVMF16BI repeat [
(const_int 1 [0x1])
])
(reg:DI 138)
(const_int 2 [0x2]) repeated x2
(const_int 1 [0x1])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(const_vector:RVVM2SF repeat [
(const_double:SF 0.0 [0x0.0p+0])
])
(unspec:RVVM2SF [
(reg:DI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.c":12:10 3943
{*pred_broadcastrvvm2sf_imm}
(expr_list:REG_DEAD (reg:DI 138)
(expr_list:REG_DEAD (reg:SI 67 vtype)
(expr_list:REG_DEAD (reg:SI 66 vl)
(expr_list:REG_DEAD (reg:DI 0 zero)
(expr_list:REG_EQUAL (const_vector:RVVM2SF repeat [
(const_double:SF 0.0 [0x0.0p+0])
])
(nil)))))))
(insn 8 18 9 2 (set (subreg:RVVM1SF (reg:RVVM2SF 134 [ <retval> ]) 0)
(reg:RVVM1SF 139)) "/app/example.c":12:10 2591 {*movrvvm1sf_whole}
(expr_list:REG_DEAD (reg:RVVM1SF 139)
(nil)))
(insn 9 8 13 2 (set (subreg:RVVM1SF (reg:RVVM2SF 134 [ <retval> ]) [16, 16])
(reg:RVVM1SF 140)) "/app/example.c":12:10 2591 {*movrvvm1sf_whole}
(expr_list:REG_DEAD (reg:RVVM1SF 140)
(nil)))
```
Confirmed. There are others like this too.
Though I wonder if we emit:
(clobber (reg:RVVM2SF 134 [ <retval> ]))
When expanding __riscv_vcreate_v_f32m1_f32m2 and friends. If that might help.
The other thing is init-reg gets in the way and adds:
```
(insn 17 16 18 2 (set (reg:DI 138)
(unspec:DI [
(const_int 8 [0x8])
] UNSPEC_VLMAX)) "/app/example.c":6:10 -1
(nil))
(insn 18 17 8 2 (set (reg:RVVM2HF 134 [ <retval> ])
(if_then_else:RVVM2HF (unspec:RVVMF8BI [
(const_vector:RVVMF8BI repeat [
(const_int 1 [0x1])
])
(reg:DI 138)
(const_int 2 [0x2]) repeated x2
(const_int 1 [0x1])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(const_vector:RVVM2HF repeat [
(const_double:HF 0.0 [0x0.0p+0])
])
(unspec:RVVM2HF [
(reg:DI 0 zero)
] UNSPEC_VUNDEF))) "/app/example.c":6:10 -1
(expr_list:REG_EQUAL (const_vector:RVVM2HF repeat [
(const_double:HF 0.0 [0x0.0p+0])
])
(nil)))
```
next prev parent reply other threads:[~2024-02-13 22:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-13 22:33 [Bug target/113913] New: " ewlu at rivosinc dot com
2024-02-13 22:54 ` pinskia at gcc dot gnu.org [this message]
2024-02-16 23:33 ` [Bug target/113913] " juzhe.zhong at rivai dot ai
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