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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3 Date: Fri, 23 Feb 2024 20:54:07 +0000 [thread overview] Message-ID: <bug-114028-4-RrMmdHDay6@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-114028-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028 --- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>: https://gcc.gnu.org/g:85c12ae8b80902ed46c97f33dbb61533e07f2905 commit r14-9159-g85c12ae8b80902ed46c97f33dbb61533e07f2905 Author: Robin Dapp <rdapp@ventanamicro.com> Date: Thu Feb 22 13:40:55 2024 +0100 RISC-V: Fix vec_init for simple sequences [PR114028]. For a vec_init (_a, _a, _a, _a) with _a of mode DImode we try to construct a "superword" of two "_a"s. This only works for modes < Pmode when we can "shift and or" both halves into one Pmode register. This patch disallows the optimization for inner_mode == Pmode and emits a simple broadcast in such a case. gcc/ChangeLog: PR target/114028 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p): Return false if inner mode is already Pmode. (rvv_builder::is_all_same_sequence): New function. (expand_vec_init): Emit broadcast if sequence is all same. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114028.c: New test.
next prev parent reply other threads:[~2024-02-23 20:54 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-21 2:39 [Bug target/114028] New: " patrick at rivosinc dot com 2024-02-21 2:41 ` [Bug target/114028] " pinskia at gcc dot gnu.org 2024-02-22 12:47 ` rdapp at gcc dot gnu.org 2024-02-23 20:54 ` cvs-commit at gcc dot gnu.org [this message] 2024-02-27 0:20 ` patrick at rivosinc dot com
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