[Bug target/114200] [14] RISC-V fixed-length vector miscompile at -O3

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114200

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:

https://gcc.gnu.org/g:59554a50be8ebbd52e8a6348a92110af182e1874

commit r14-9345-g59554a50be8ebbd52e8a6348a92110af182e1874
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Wed Mar 6 12:15:40 2024 +0100

    RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].

    Three-operand instructions like vmacc are modeled with an implicit
    output reload when the output does not match one of the operands.  For
    this we use vmv.v.v which is subject to length masking.

    In a situation where the current vl is less than the full vlenb
    and the fma's result value is used as input for a vector reduction
    (which is never length masked) we effectively only reduce vl
    elements.  The masked-out elements are relevant for the
    reduction, though, leading to a wrong result.

    This patch replaces the vmv reloads by full-register reloads.

    gcc/ChangeLog:

            PR target/114200
            PR target/114202

            * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr114200.c: New test.
            * gcc.target/riscv/rvv/autovec/pr114202.c: New test.