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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug ipa/114247] RISC-V: miscompile at -O3 and IPA SRA
Date: Tue, 05 Mar 2024 23:29:09 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114247

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
           Keywords|                            |ABI
   Last reconfirmed|                            |2024-03-05
          Component|target                      |ipa
     Ever confirmed|0                           |1
            Summary|RISC-V: miscompile at -O3   |RISC-V: miscompile at -O3
                   |                            |and IPA SRA

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
I think this is an IPA SRA issue.

The IR looks like:
  j.constprop.isra (65535);

That is wrong for signed short ...


If I try manually I get:
  j12 (-1);


```
void j.constprop.isra (short int ISRA.10)
{
...
}
```


IS there another target where the upper bits of the register are defined?=