From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id B3FB338582A3; Wed, 6 Mar 2024 12:37:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B3FB338582A3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1709728621; bh=zYNvnasKGMAs501mSLUZdCsiTkMuSp8QpKvrmPLV43M=; h=From:To:Subject:Date:In-Reply-To:References:From; b=UCcXxNlNMKe9aCI24HzrspqMnc1AYFFK8fmbIAmjuXmI+jdhSa3u+ALNJAfxh3pgM scRTaliJuI+5JfA+ASDlz1hh1HhNCaCkMROMg1Ok4EZX20apYNE4aUTtYdHJDG5Z07 RCkYOw2I3R/qwZLGhZ2tT08he1qrtveMX3Yo6Mgo= From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114252] Introducing bswapsi reduces code performance Date: Wed, 06 Mar 2024 12:37:01 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114252 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |rguenth at gcc dot gnu.org, | |vmakarov at gcc dot gnu.org --- Comment #4 from Richard Biener --- Yes, the missing "detail" for the middle-end is that the uint32_t is actual= ly 4 separate byte registers. And the 'int' argument to bswap32 requires 4 registers as well. So bswap on a value is just register shuffling, right? And thus this libcall will never be better than doing it inline as you probably cannot expect the incoming arguments and the outgoing return registers to be allocated in a way so no reg-reg moves remain? Of course since it's still SImode pseudos on RTL you might want to write an expander that populates 4 QImode pseudos from the SImode one and composes that back to a byte-swapped SImode one. Hoping register allocation can then elide everything again? I'd try to avoid using subregs if possible though using those would be easi= est I think (but you might fall foul of RA similar to -fsplit-wide-types). Shifts and truncates/zero_extends are possibly superior. Who knows. Or split it only after reload and have the pattern consume one scratch you need for the register-register moves. Hey, maybe the RA itself can know how to allocate a bswap:SI optimally and "reload" it to be reg-reg moves ...=