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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/114310] [11/12/13/14 Regression] [aarch64]
 __sync_val_compare_and_swap fails on __int128_t with newval = 0
Date: Thu, 14 Mar 2024 13:10:00 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114310

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:9349aefa1df7ae36714b7b9f426ad46e314892d1

commit r14-9469-g9349aefa1df7ae36714b7b9f426ad46e314892d1
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Mar 14 14:09:20 2024 +0100

    aarch64: Fix TImode __sync_*_compare_and_exchange expansion with LSE
[PR114310]

    The following testcase ICEs with LSE atomics.
    The problem is that the @atomic_compare_and_swap<mode> expander uses
    aarch64_reg_or_zero predicate for the desired operand, which is fine,
    given that for most of the modes and even for TImode in some cases
    it can handle zero immediate just fine, but the TImode
    @aarch64_compare_and_swap<mode>_lse just uses register_operand for
    that operand instead, again intentionally so, because the casp,
    caspa, caspl and caspal instructions need to use a pair of consecutive
    registers for the operand and xzr is just one register and we can't
    just store zero into the link register to emulate pair of zeros.

    So, the following patch fixes that by forcing the newval operand into
    a register for the TImode LSE case.

    2024-03-14  Jakub Jelinek  <jakub@redhat.com>

            PR target/114310
            * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): =
For
            TImode force newval into a register.

            * gcc.dg/pr114310.c: New test.=