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From: "tnfchris at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug tree-optimization/114345] FRE missing knowledge of semantics of IFN loads
Date: Fri, 15 Mar 2024 08:32:22 +0000 [thread overview]
Message-ID: <bug-114345-4-BGrRNClHVx@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-114345-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114345
--- Comment #5 from Tamar Christina <tnfchris at gcc dot gnu.org> ---
(In reply to Richard Biener from comment #4)
> Well, the shuffling in .LOAD_LANES will be a bit awkward to do, but sure. We
> basically lack "constant folding" of .LOAD_LANES and similarly of course
> we can't see through .STORE_LANES of a constant when later folding a scalar
> load from the same memory.
I guess it becomes harder with the 3 and 4 lane ones, but the 2 lanes one is
just a single VEC_PERM_EXPR no?
next prev parent reply other threads:[~2024-03-15 8:32 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-15 4:06 [Bug tree-optimization/114345] New: " tnfchris at gcc dot gnu.org
2024-03-15 4:11 ` [Bug tree-optimization/114345] " pinskia at gcc dot gnu.org
2024-03-15 4:17 ` pinskia at gcc dot gnu.org
2024-03-15 7:42 ` tnfchris at gcc dot gnu.org
2024-03-15 8:30 ` rguenth at gcc dot gnu.org
2024-03-15 8:32 ` tnfchris at gcc dot gnu.org [this message]
2024-03-15 8:51 ` rguenther at suse dot de
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