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From: "pan2.li at intel dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug c/114352] New: RISC-V: ICE when
 __attribute__((target("arch=+v")) and build with rv64gc -O3
Date: Fri, 15 Mar 2024 08:25:00 +0000
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X-Bugzilla-Product: gcc
X-Bugzilla-Component: c
X-Bugzilla-Version: 14.0
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X-Bugzilla-Severity: normal
X-Bugzilla-Who: pan2.li at intel dot com
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114352

            Bug ID: 114352
           Summary: RISC-V: ICE when __attribute__((target("arch=3D+v")) and
                    build with rv64gc -O3
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pan2.li at intel dot com
  Target Milestone: ---

Assume we have a sample code as below

void
__attribute__((target("arch=3D+v")))
add (int *a, int *b, int *out, unsigned count)
{
  unsigned i;

  for (i =3D 0; i < count; i++)
    out[i] =3D a[i] + b[i];
}

When build with -march=3Drv64gc -O3 there will be ICE as below:
test.c: In function =E2=80=98add=E2=80=99:
test.c:4:1: internal compiler error: Floating point exception=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20
                                                     4 | {
      | ^=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20
                                                 0x1a5891b crash_signal=20=
=20=20=20=20=20=20=20
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/toplev.cc=
:319
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20
                                         0x7f0a7884251f ???
        ./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0x1f51ba4 riscv_hard_regno_nregs
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/config/ri=
scv/riscv.cc:8143
0x1967bb9 init_reg_modes_target()
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/reginfo.c=
c:471
0x13fc029 init_emit_regs()
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/emit-rtl.=
cc:6237
0x1a5b83d target_reinit()
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/toplev.cc=
:1936
0x35e374d save_target_globals()
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/target-gl=
obals.cc:92
0x35e381f save_target_globals_default_opts()
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/target-gl=
obals.cc:122
0x1f544cc riscv_save_restore_target_globals(tree_node*)
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/config/ri=
scv/riscv.cc:9138
0x1f55c36 riscv_set_current_function
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/config/ri=
scv/riscv.cc:9477
0x1505be7 invoke_set_current_function_hook
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/function.=
cc:4690
0x1505f60 allocate_struct_function(tree_node*, bool)
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/function.=
cc:4813
0x1044e33 store_parm_decls()
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-decl.=
cc:11084
0x10b8a54 c_parser_declaration_or_fndef
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parse=
r.cc:2975
0x10b62b7 c_parser_external_declaration
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parse=
r.cc:2046
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20
                                    0x10b5d2a c_parser_translation_unit
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parse=
r.cc:1900
0x110d5f4 c_parse_file()
=20=20=20=20=20=20=20
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parse=
r.cc:26889
0x11bd3f3 c_common_parse_file()

Prepare a script for most vector arch combinations we will have:
arch=3D+v Fail
arch=3D+zve32x Fail
arch=3D+zve32f Fail
arch=3D+zve64x Fail
arch=3D+zve64f Fail
arch=3D+zve64d Fail
arch=3D+zvl64b Pass
arch=3D+zvl128b Pass
arch=3D+zvl256b Pass
arch=3D+zvl4096b Pass
arch=3D+zve32x_zvl64b Fail
arch=3D+zve32x_zvl128b Fail
arch=3D+zve32x_zvl256b Fail
arch=3D+zve32x_zvl4096b Fail
arch=3D+zve32f_zvl64b Fail
arch=3D+zve32f_zvl128b Fail
arch=3D+zve32f_zvl256b Fail
arch=3D+zve32f_zvl4096b Fail
arch=3D+zve64x_zvl64b Fail
arch=3D+zve64x_zvl128b Fail
arch=3D+zve64x_zvl256b Fail
arch=3D+zve64x_zvl4096b Fail
arch=3D+zve64f_zvl64b Fail
arch=3D+zve64f_zvl128b Fail
arch=3D+zve64f_zvl256b Fail
arch=3D+zve64f_zvl4096b Fail
arch=3D+zve64d_zvl64b Fail
arch=3D+zve64d_zvl128b Fail
arch=3D+zve64d_zvl256b Fail
arch=3D+zve64d_zvl4096b Fail

The passed arch cannot vectorized but the -march=3Darmv8-a -O3 with
__attribute__((target("+sve2"))) can vectorize.

I will try to fix this ICE soon.=