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From: "Explorer09 at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114490] Optimization: x86 "shl" condition codes never
 reused
Date: Wed, 27 Mar 2024 11:28:20 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114490

--- Comment #4 from Kang-Che Sung <Explorer09 at gmail dot com> ---
1. I just read "AMD64 Architecture Programmer's Manual - Volume 3:
General-Purpose and System Instructions"
(https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/progr=
ammer-references/24594.pdf)

It has a clearer wording in the "SAL / SHL" section:

"If the shift count is 0, no flags are modified."

Just mention for reference.

2. I still don't believe there is no chance of optimizing this thing, but it
requires GCC to track the state of the FLAGS register. I don't know if GCC =
can
do this internally. If GCC can't do this for now, that's OK for me (the exa=
mple
I posted can be rewritten to another pattern that might produce even smaller
code in x86). But maybe label this as a WONTFIX and not INVALID?=