From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id E11773847725; Wed, 3 Apr 2024 22:39:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E11773847725 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1712183956; bh=mIeIMhknU+jX//9Cdl/u0W2AYzl3S9S/jDG7YLuQiic=; h=From:To:Subject:Date:In-Reply-To:References:From; b=MAyU81p6YaddNwk9ibrw/HRX976+sjfYhkGvG+UWnD52ORDLzgmjANtYhJgogIHUK CexgaXjvTTKaLvssvPGi2LCvanbZN6Us6FdoCLZwAfo51CxalghS+i92PGOME/C3hI SkIg6EiKhAWd0X2dJR+sY2FJqahOZZgnM6LSyKio= From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114576] [14 regression]VEX-prefixed AES instruction without AVX enabled Date: Wed, 03 Apr 2024 22:39:16 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114576 Jakub Jelinek changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |jakub at gcc dot gnu.org --- Comment #3 from Jakub Jelinek --- (In reply to Andrew Pinski from comment #2) > Something like this should fix it (but I am not 100% sure it is correct n= or > can I test it): This is IMHO not correct. vaesenc etc. instructions can be used even if just -maes -mavx, not just -m= vaes -mavx512vl. But, it is especially messy because -mvaes doesn't imply -maes, so IMHO if somebody e.g. asks for -mvaes -mavx512vl -mno-aes and the insns don't use a= ny xmm16+ register, it would emit the insn using VEX encoding rather than EVEX= , so I think we need to use {evex} prefixes. So I think we want: --- gcc/config/i386/i386.md.jj 2024-03-18 10:33:27.983419363 +0100 +++ gcc/config/i386/i386.md 2024-04-04 00:17:48.818340648 +0200 @@ -568,13 +568,14 @@ (define_attr "unit" "integer,i387,sse,mm ;; Used to control the "enabled" attribute on a per-instruction basis. (define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx, - x64_avx,x64_avx512bw,x64_avx512dq,aes,apx_ndd, + x64_avx,x64_avx512bw,x64_avx512dq,apx_ndd, sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noa= vx, =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,avx512f_512, noavx512f,avx512bw,avx512bw_512,noavx512bw,avx512dq, noavx512dq,fma_or_avx512vl,avx512vl,noavx512vl,avxvnni, avx512vnnivl,avx512fp16,avxifma,avx512ifmavl,avxneconve= rt, - avx512bf16vl,vpclmulqdqvl,avx_noavx512f,avx_noavx512vl" + avx512bf16vl,vpclmulqdqvl,avx_noavx512f,avx_noavx512vl, + aes_avx,vaes_avx512vl" (const_string "base")) ;; The (bounding maximum) length of an instruction immediate. @@ -915,7 +916,6 @@ (define_attr "enabled" "" (symbol_ref "TARGET_64BIT && TARGET_AVX512BW") (eq_attr "isa" "x64_avx512dq") (symbol_ref "TARGET_64BIT && TARGET_AVX512DQ") - (eq_attr "isa" "aes") (symbol_ref "TARGET_AES") (eq_attr "isa" "sse_noavx") (symbol_ref "TARGET_SSE && !TARGET_AVX") (eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2") @@ -968,6 +968,10 @@ (define_attr "enabled" "" (symbol_ref "TARGET_VPCLMULQDQ && TARGET_AVX512VL") (eq_attr "isa" "apx_ndd") (symbol_ref "TARGET_APX_NDD") + (eq_attr "isa" "aes_avx") + (symbol_ref "TARGET_AES && TARGET_AVX") + (eq_attr "isa" "vaes_avx512vl") + (symbol_ref "TARGET_VAES && TARGET_AVX512VL") (eq_attr "mmx_isa" "native") (symbol_ref "!TARGET_MMX_WITH_SSE") --- gcc/config/i386/sse.md.jj 2024-03-18 08:58:45.942772799 +0100 +++ gcc/config/i386/sse.md 2024-04-04 00:33:32.386194779 +0200 @@ -26277,75 +26277,79 @@ (define_insn "xop_vpermil23" ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_insn "aesenc" - [(set (match_operand:V2DI 0 "register_operand" "=3Dx,x,v") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") - (match_operand:V2DI 2 "vector_operand" "xja,xm,vm")] + [(set (match_operand:V2DI 0 "register_operand" "=3Dx,x,x,v") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,x,v") + (match_operand:V2DI 2 "vector_operand" "xja,xm,xm,vm= ")] UNSPEC_AESENC))] "TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)" "@ aesenc\t{%2, %0|%0, %2} vaesenc\t{%2, %1, %0|%0, %1, %2} + %{evex%} vaesenc\t{%2, %1, %0|%0, %1, %2} vaesenc\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,aes,avx512vl") + [(set_attr "isa" "noavx,aes_avx,vaes_avx512vl,vaes_avx512vl") (set_attr "type" "sselog1") - (set_attr "addr" "gpr16,*,*") + (set_attr "addr" "gpr16,*,*,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,vex,evex") - (set_attr "btver2_decode" "double,double,double") + (set_attr "prefix" "orig,vex,evex,evex") + (set_attr "btver2_decode" "double,double,double,double") (set_attr "mode" "TI")]) (define_insn "aesenclast" - [(set (match_operand:V2DI 0 "register_operand" "=3Dx,x,v") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") - (match_operand:V2DI 2 "vector_operand" "xja,xm,vm")] + [(set (match_operand:V2DI 0 "register_operand" "=3Dx,x,x,v") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,x,v") + (match_operand:V2DI 2 "vector_operand" "xja,xm,xm,vm= ")] UNSPEC_AESENCLAST))] "TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)" "@ aesenclast\t{%2, %0|%0, %2} vaesenclast\t{%2, %1, %0|%0, %1, %2} + %{evex%} vaesenclast\t{%2, %1, %0|%0, %1, %2} vaesenclast\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,aes,avx512vl") + [(set_attr "isa" "noavx,aes_avx,vaes_avx512vl,vaes_avx512vl") (set_attr "type" "sselog1") - (set_attr "addr" "gpr16,*,*") + (set_attr "addr" "gpr16,*,*,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,vex,evex") - (set_attr "btver2_decode" "double,double,double")=20 + (set_attr "prefix" "orig,vex,evex,evex") + (set_attr "btver2_decode" "double,double,double,double") (set_attr "mode" "TI")]) (define_insn "aesdec" - [(set (match_operand:V2DI 0 "register_operand" "=3Dx,x,v") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") - (match_operand:V2DI 2 "vector_operand" "xja,xm,vm")] + [(set (match_operand:V2DI 0 "register_operand" "=3Dx,x,x,v") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,x,v") + (match_operand:V2DI 2 "vector_operand" "xja,xm,xm,vm= ")] UNSPEC_AESDEC))] "TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)" "@ aesdec\t{%2, %0|%0, %2} vaesdec\t{%2, %1, %0|%0, %1, %2} + %{evex%} vaesdec\t{%2, %1, %0|%0, %1, %2} vaesdec\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,aes,avx512vl") + [(set_attr "isa" "noavx,aes_avx,vaes_avx512vl,vaes_avx512vl") (set_attr "type" "sselog1") - (set_attr "addr" "gpr16,*,*") + (set_attr "addr" "gpr16,*,*,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,vex,evex") - (set_attr "btver2_decode" "double,double,double")=20 + (set_attr "prefix" "orig,vex,evex,evex") + (set_attr "btver2_decode" "double,double,double,double")=20 (set_attr "mode" "TI")]) (define_insn "aesdeclast" - [(set (match_operand:V2DI 0 "register_operand" "=3Dx,x,v") - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") - (match_operand:V2DI 2 "vector_operand" "xja,xm,vm")] + [(set (match_operand:V2DI 0 "register_operand" "=3Dx,x,x,v") + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,x,v") + (match_operand:V2DI 2 "vector_operand" "xja,xm,xm,vm= ")] UNSPEC_AESDECLAST))] "TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)" "@ aesdeclast\t{%2, %0|%0, %2} vaesdeclast\t{%2, %1, %0|%0, %1, %2} + %{evex%} vaesdeclast\t{%2, %1, %0|%0, %1, %2} vaesdeclast\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,aes,avx512vl") - (set_attr "addr" "gpr16,*,*") + [(set_attr "isa" "noavx,aes_avx,vaes_avx512vl,vaes_avx512vl") + (set_attr "addr" "gpr16,*,*,*") (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,vex,evex") - (set_attr "btver2_decode" "double,double,double") + (set_attr "prefix" "orig,vex,evex,evex") + (set_attr "btver2_decode" "double,double,double,double") (set_attr "mode" "TI")]) (define_insn "aesimc" @@ -30246,24 +30250,32 @@ (define_insn "vpdpwssds__maskz_1" [(set_attr ("prefix") ("evex"))]) (define_insn "vaesdec_" - [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=3Dv") + [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=3Dx,v") (unspec:VI1_AVX512VL_F - [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v") - (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")] + [(match_operand:VI1_AVX512VL_F 1 "register_operand" "x,v") + (match_operand:VI1_AVX512VL_F 2 "vector_operand" "xm,vm")] UNSPEC_VAESDEC))] "TARGET_VAES" - "vaesdec\t{%2, %1, %0|%0, %1, %2}" -) +{ + if (which_alternative =3D=3D 0 && mode =3D=3D V16QImode) + return "%{evex%} vaesdec\t{%2, %1, %0|%0, %1, %2}"; + else + return "vaesdec\t{%2, %1, %0|%0, %1, %2}"; +}) (define_insn "vaesdeclast_" - [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=3Dv") + [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=3Dx,v") (unspec:VI1_AVX512VL_F - [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v") - (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")] + [(match_operand:VI1_AVX512VL_F 1 "register_operand" "x,v") + (match_operand:VI1_AVX512VL_F 2 "vector_operand" "xm,vm")] UNSPEC_VAESDECLAST))] "TARGET_VAES" - "vaesdeclast\t{%2, %1, %0|%0, %1, %2}" -) +{ + if (which_alternative =3D=3D 0 && mode =3D=3D V16QImode) + return "%{evex%} vaesdeclast\t{%2, %1, %0|%0, %1, %2}"; + else + return "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"; +}) (define_insn "vaesenc_" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=3Dv") @@ -30272,18 +30284,26 @@ (define_insn "vaesenc_" (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")] UNSPEC_VAESENC))] "TARGET_VAES" - "vaesenc\t{%2, %1, %0|%0, %1, %2}" -) +{ + if (which_alternative =3D=3D 0 && mode =3D=3D V16QImode) + return "%{evex%} vaesenc\t{%2, %1, %0|%0, %1, %2}"; + else + return "vaesenc\t{%2, %1, %0|%0, %1, %2}"; +}) (define_insn "vaesenclast_" - [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=3Dv") + [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=3Dx,v") (unspec:VI1_AVX512VL_F - [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v") - (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")] + [(match_operand:VI1_AVX512VL_F 1 "register_operand" "x,v") + (match_operand:VI1_AVX512VL_F 2 "vector_operand" "xm,vm")] UNSPEC_VAESENCLAST))] "TARGET_VAES" - "vaesenclast\t{%2, %1, %0|%0, %1, %2}" -) +{ + if (which_alternative =3D=3D 0 && mode =3D=3D V16QImode) + return "%{evex%} vaesenclast\t{%2, %1, %0|%0, %1, %2}"; + else + return "vaesenclast\t{%2, %1, %0|%0, %1, %2}"; +}) (define_insn "vpclmulqdq_" [(set (match_operand:VI8_FVL 0 "register_operand" "=3Dv")=