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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114591] [12/13/14 Regression] register allocators
 introduce an extra load operation since gcc-12
Date: Wed, 10 Apr 2024 08:36:04 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114591

--- Comment #6 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
LRA starts with this:

    5: r98:SI=3D[`v1']
      REG_EQUIV [`v1']
    6: [`v2']=3Dzero_extend(r98:SI)
    7: r101:HI=3Dr98:SI#0
      REG_DEAD r98:SI
   12: ax:HI=3Dr101:HI
      REG_DEAD r101:HI
   13: use ax:HI

then decides that:

      Removing equiv init insn 5 (freq=3D1000)
    5: r98:SI=3D[`v1']
      REG_EQUIV [`v1']

and substitutes all follow-up usages of r98 with a memory access. In insn 6=
, we
have:

(mem/c:SI (symbol_ref:DI ("v1")))

while in insn 7 we have:

(mem/c:HI (symbol_ref:DI ("v1")))

It looks that different modes of memory read confuse LRA to not CSE the rea=
d.

IMO, if the preloaded value is later accessed in different modes, LRA should
leave it. Alternatively, LRA should CSE memory accesses in different modes.

Cc LRA expert ... oh, he already is in the loop.=