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From: "liuhongt at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114591] [12/13/14 Regression] register allocators
 introduce an extra load operation since gcc-12
Date: Wed, 10 Apr 2024 08:52:06 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114591

--- Comment #9 from Hongtao Liu <liuhongt at gcc dot gnu.org> ---

>=20
> It looks that different modes of memory read confuse LRA to not CSE the r=
ead.
>=20
> IMO, if the preloaded value is later accessed in different modes, LRA sho=
uld
> leave it. Alternatively, LRA should CSE memory accesses in different mode=
s.

(insn 7 6 12 2 (set (reg:HI 101 [ _5 ])
        (subreg:HI (reg:SI 98 [ v1.0_1 ]) 0)) "test.c":6:12 86
{*movhi_internal}
     (expr_list:REG_DEAD (reg:SI 98 [ v1.0_1 ])
        (nil)))

May be we should reduce cost from simple move instruction(with subreg?) when
calculating total_cost, since it's probably be eliminated by later rtl
optimization.=