From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id A267C385841F; Thu, 11 Apr 2024 06:33:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A267C385841F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1712817202; bh=1aDy/BCwb8nzUID4MMkWTz/yZLWOQUyDZeKBePgNLJ4=; h=From:To:Subject:Date:In-Reply-To:References:From; b=M+YDx/JPMiFQDzpHQeZI4FrnFV2z5soFwKhVA2+jeg5Wo/8lU82g/zbY0SgUc8J8/ BOeV9/KGTp2X8u2t1nWBVA5mL0w6cWMlpcbJi1a7dqNy60ZCEtl6ay91IT4sJsCqSR p9dM8xdOQC3JFeBHRsOVJMLw4XzcOOWyZ4TC5+uQ= From: "liuhongt at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114591] [12/13/14 Regression] register allocators introduce an extra load operation since gcc-12 Date: Thu, 11 Apr 2024 06:33:21 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.2.0 X-Bugzilla-Keywords: missed-optimization, ra X-Bugzilla-Severity: normal X-Bugzilla-Who: liuhongt at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.4 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114591 --- Comment #12 from Hongtao Liu --- short a; short c; short d; void foo (short b, short f) { c =3D b + a; d =3D f + a; } foo(short, short): addw a(%rip), %di addw a(%rip), %si movw %di, c(%rip) movw %si, d(%rip) ret this one is bad since gcc10.1 and there's no subreg, The problem is if the operand is used by more than 1 insn, and they all support separate m constraint, mem_cost is quite small(just 1, reg move cost is 2), and this m= akes RA more inclined to propagate memory across insns. I guess RA assumes the separate m means the insn only support memory_operand? 961 if (op_class =3D=3D NO_REGS) 962 /* Although we don't need insn to reload from 963 memory, still accessing memory is usually more 964 expensive than a register. */ 965 pp->mem_cost =3D frequency; 966 else=