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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114639] [riscv] ICE in create_pre_exit, at
 mode-switching.cc:451
Date: Mon, 22 Apr 2024 22:53:54 +0000
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X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: ice-on-valid-code
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X-Bugzilla-Who: juzhe.zhong at rivai dot ai
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X-Bugzilla-Resolution: FIXED
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114639

--- Comment #16 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
This issue is not fully fixed since the fixed patch only fixes ICE but ther=
e is
a regression in codegen:

https://godbolt.org/z/4nvxeqb6K

Terrible codege:

test(__rvv_uint64m4_t):
        addi    sp,sp,-16
        csrr    t0,vlenb
        sd      ra,8(sp)
        sub     sp,sp,t0
        vs1r.v  v1,0(sp)
        sub     sp,sp,t0
        vs1r.v  v2,0(sp)
        sub     sp,sp,t0
        vs1r.v  v3,0(sp)
        sub     sp,sp,t0
        vs1r.v  v4,0(sp)
        sub     sp,sp,t0
        vs1r.v  v5,0(sp)
        sub     sp,sp,t0
        vs1r.v  v6,0(sp)
        sub     sp,sp,t0
        vs1r.v  v7,0(sp)
        sub     sp,sp,t0
        vs1r.v  v24,0(sp)
        sub     sp,sp,t0
        vs1r.v  v25,0(sp)
        sub     sp,sp,t0
        vs1r.v  v26,0(sp)
        sub     sp,sp,t0
        vs1r.v  v27,0(sp)
        sub     sp,sp,t0
        vs1r.v  v28,0(sp)
        sub     sp,sp,t0
        vs1r.v  v29,0(sp)
        sub     sp,sp,t0
        vs1r.v  v30,0(sp)
        sub     sp,sp,t0
        csrr    t0,vlenb
        slli    t1,t0,2
        vs1r.v  v31,0(sp)
        sub     sp,sp,t1
        vs4r.v  v8,0(sp)
        call    get_vl()
        csrr    t0,vlenb
        slli    t1,t0,2
        vl4re64.v       v8,0(sp)
        csrr    t0,vlenb
        add     sp,sp,t1
        vl1re64.v       v31,0(sp)
        add     sp,sp,t0
        vl1re64.v       v30,0(sp)
        add     sp,sp,t0
        vl1re64.v       v29,0(sp)
        add     sp,sp,t0
        vl1re64.v       v28,0(sp)
        add     sp,sp,t0
        vl1re64.v       v27,0(sp)
        add     sp,sp,t0
        vl1re64.v       v26,0(sp)
        add     sp,sp,t0
        vl1re64.v       v25,0(sp)
        add     sp,sp,t0
        vl1re64.v       v24,0(sp)
        add     sp,sp,t0
        vl1re64.v       v7,0(sp)
        add     sp,sp,t0
        vl1re64.v       v6,0(sp)
        add     sp,sp,t0
        vl1re64.v       v5,0(sp)
        add     sp,sp,t0
        vl1re64.v       v4,0(sp)
        add     sp,sp,t0
        vl1re64.v       v3,0(sp)
        add     sp,sp,t0
        vl1re64.v       v2,0(sp)
        add     sp,sp,t0
        vl1re64.v       v1,0(sp)
        add     sp,sp,t0
        ld      ra,8(sp)
        vsetvli zero,a0,e64,m4,ta,ma
        vmsne.vi        v0,v8,0
        addi    sp,sp,16
        jr      ra=