From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id D7E0F3861871; Tue, 9 Apr 2024 01:33:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D7E0F3861871 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1712626395; bh=xuJ/k25y/jmBBQ63XNb94P8r6ehGx/x06gvQ9tjLQ/I=; h=From:To:Subject:Date:In-Reply-To:References:From; b=YQ7oLtzVPZrLgktOMykZw/iSwuQhoBOmFh8g5ioAbek/xBpHFLzJg8yTaKFtGvoBZ xNhLpwB+HW4tIK743vApvwNRzTbPD6t3DW1NbDsp0rjvMfSzNHzJ8vAJ4OpBxw8Ai5 X7vxZCYjLyOL4UOLjvb61/aYPilBxSDDMK+zxsLY= From: "pan2.li at intel dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114639] [riscv] ICE in create_pre_exit, at mode-switching.cc:451 Date: Tue, 09 Apr 2024 01:33:15 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: pan2.li at intel dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114639 --- Comment #5 from Li Pan --- (In reply to Kito Cheng from comment #4) > Reduced case: > ```c > typedef long c; > #pragma riscv intrinsic "vector" > template struct d {}; > struct e { > using f =3D d<0>; > }; > struct g { > using f =3D e::f; > }; > template using h =3D g::f; > template long k(d); > vbool16_t j(vuint64m4_t a) { > c b; > return __riscv_vmsne_vx_u64m4_b16(a, b, k(h())); > } >=20 > ``` Thanks Kito, reproduced on reduced case with option "riscv64-unknown-elf-g++ -O2 -march=3Drv64gcv". will take a look into it. during RTL pass: mode_sw test.c: In function =E2=80=98vbool16_t j(vuint64m4_t)=E2=80=99: test.c:15:1: internal compiler error: in create_pre_exit, at mode-switching.cc:451 15 | } | ^ 0x3978f12 create_pre_exit=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20 /home/pli/gcc/555/riscv-gnu-toolchain/gcc/__RISCV_BUILD__/../gcc/mode-switc= hing.cc:451 0x3979e9e optimize_mode_switching =20=20=20=20=20=20=20 /home/pli/gcc/555/riscv-gnu-toolchain/gcc/__RISCV_BUILD__/../gcc/mode-switc= hing.cc:849 0x397b9bc execute =20=20=20=20=20=20=20 /home/pli/gcc/555/riscv-gnu-toolchain/gcc/__RISCV_BUILD__/../gcc/mode-switc= hing.cc:1324 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See for instructions.=