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Subject: [Bug target/114668] [14] RISC-V rv64gcv: miscompile at -O3
Date: Mon, 15 Apr 2024 13:12:27 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114668

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:

https://gcc.gnu.org/g:02cc8f3e68f9af96d484d9946ceaa9e3eed38151

commit r14-9972-g02cc8f3e68f9af96d484d9946ceaa9e3eed38151
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Mon Apr 15 12:44:56 2024 +0200

    RISC-V: Add VLS to mask vec_extract [PR114668].

    This adds the missing VLS modes to the mask extract expanders.

    gcc/ChangeLog:

            PR target/114668

            * config/riscv/autovec.md: Add VLS.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr114668.c: New test.=