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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114668] [14] RISC-V rv64gcv: miscompile at -O3
Date: Tue, 09 Apr 2024 22:00:24 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114668

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Looks to be working on aarch64 (both with/without SVE):
```
[apinski@xeond2 upstream-cross-aarch64]$ ./install/bin/aarch64-linux-gnu-gcc
-O3 -fno-vect-cost-model t6.c -static -fno-vect-cost-model
[apinski@xeond2 upstream-cross-aarch64]$ ./install-qemu/bin/qemu-aarch64 a.=
out
1
1
[apinski@xeond2 upstream-cross-aarch64]$ ./install/bin/aarch64-linux-gnu-gcc
-O3 -fno-vect-cost-model t6.c -static -march=3Darmv9-a+sve -fno-vect-cost-m=
odel
[apinski@xeond2 upstream-cross-aarch64]$ ./install-qemu/bin/qemu-aarch64 a.=
out
1
1

```=