[Bug target/114696] ICE: in extract_constrain_insn_cached, at recog.cc:2725 insn does not satisfy its constraints: {*anddi_1} with -mapxf -mx32

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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114696

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by H.J. Lu <hjl@gcc.gnu.org>:

https://gcc.gnu.org/g:a3281dd0f4b46c16ec1192ad411c0a96e6d086eb

commit r14-9970-ga3281dd0f4b46c16ec1192ad411c0a96e6d086eb
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Fri Apr 12 15:42:12 2024 -0700

    x86: Allow TImode offsettable memory only with 8-bit constant

    The x86 instruction size limit is 15 bytes.  If a NDD instruction has
    a segment prefix byte, a 4-byte opcode prefix, a MODRM byte, a SIB byte,
    a 4-byte displacement and a 4-byte immediate, adding an address size
    prefix will exceed the size limit.  Change TImode ADD, AND, OR and XOR
    to allow offsettable memory only with 8-bit signed integer constant,
    which is encoded with a 1-byte immediate, if the address size prefix
    is used.

    gcc/

            PR target/114696
            * config/i386/i386.md (isa): Add apx_ndd_64.
            (enabled): Likewise.
            (*add<dwi>3_doubleword): Change rjO to r,ro,jO with 8-bit
            signed integer constant and enable jO only for apx_ndd_64.
            (*add<dwi>3_doubleword_cc_overflow_1): Likewise.
            (*and<dwi>3_doubleword): Likewise.
            (*<code><dwi>3_doubleword): Likewise.

    gcc/testsuite/

            PR target/114696
            * gcc.target/i386/apx-ndd-x32-2a.c: New test.
            * gcc.target/i386/apx-ndd-x32-2b.c: Likewise.
            * gcc.target/i386/apx-ndd-x32-2c.c: Likewise.
            * gcc.target/i386/apx-ndd-x32-2d.c: Likewise.