From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 15CA53858D35; Mon, 15 Apr 2024 10:30:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 15CA53858D35 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713177058; bh=Ixzadu3BR+fHwdgczxNVM49pbPlCeSDKdClpi3yCddM=; h=From:To:Subject:Date:In-Reply-To:References:From; b=RTIg7DYcbajDDeNP06r4zRtOd2uN4PAUI95dNP8LxCsyWEm3IyBKPFT8SQLQVcwbx gfyZh5OyUibK4iZHyLG/b4NnN2zpea86vE87J2Mz0KqbO9F60snbG6xkasor8y/JZJ Ho78a0u/SRMvg+Y8GGAHAszqH5ZsqBXl3movFbac= From: "pan2.li at intel dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114714] [RISC-V][RVV] ICE: insn does not satisfy its constraints (postreload) Date: Mon, 15 Apr 2024 10:30:57 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: pan2.li at intel dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114714 --- Comment #2 from Li Pan --- The vzext.vf2 has earlyclobber dest operand, and then it cannot allocated to the source operand, like vzext.vf2 v0, v0. Thus we will fail when check_rt= l. (define_insn "@pred__vf2" [(set (match_operand:VWEXTI 0 "register_operand" "=3Dvd, = vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") ........(if_then_else:VWEXTI ........ (unspec: ........ [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") ........ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") ........ (match_operand 5 "const_int_operand" "i, i, = i,=20 i, i, i, i, i, i, i, i, i, i, i") ........ (match_operand 6 "const_int_operand" "i, i, = i,=20 i, i, i, i, i, i, i, i, i, i, i") ........ (match_operand 7 "const_int_operand" "i, i, = i,=20 i, i, i, i, i, i, i, i, i, i, i") ........ (reg:SI VL_REGNUM) ........ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) ........ (any_extend:VWEXTI ........ (match_operand: 3 "register_operand"=20=20 "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) ........ (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu= ,=20 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] "TARGET_VECTOR" "vext.vf2\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")]) ---------------------------------------------------------------------------= ------------------------- insn 1205 1214 5405 70 (set (reg:RVVM1SI 97 v1 [orig:687 _1177 ] [687]) (if_then_else:RVVM1SI (unspec:RVVMF32BI [ (const_vector:RVVMF32BI repeat [ (const_int 1 [0x1]) ]) (reg:DI 25 s9 [orig:539 _889 ] [539]) (const_int 2 [0x2]) repeated x2 (const_int 0 [0]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (zero_extend:RVVM1SI (reg:RVVMF2HI 97 v1 [orig:654 _1100 ] [654= ])) (unspec:RVVM1SI [ (reg:DI 0 zero) ] UNSPEC_VUNDEF))) "../hwy/ops/rvv-inl.h":1964:386 discrim 1 8452 {pred_zero_extendrvvm1si_vf2} (nil)) during RTL pass: reload=