From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id EDA223858404; Mon, 22 Apr 2024 12:57:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EDA223858404 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713790620; bh=vKe+uH9lfbzfmXP2BSWzVMOEjoRUSdD/BeqOq365hmY=; h=From:To:Subject:Date:In-Reply-To:References:From; b=Nmjsnz+mPqLmwS19LOoFvUvsTtrI6EDfHBJdscjyb81SlbUyKVB04DFenh+OxWsbV ub+o9cB3wYQ47m+jJt3CJuti9rvCUtFVuaxBNCYzML9I2qfd/gCa8dQoQQVBFR+1a2 jiBCFbC+qpFLN7Te2U5bM+nS6iuuJW7glHn51Rz4= From: "rdapp at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114714] [RISC-V][RVV] ICE: insn does not satisfy its constraints (postreload) Date: Mon, 22 Apr 2024 12:56:58 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: rdapp at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114714 Robin Dapp changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |rdapp at gcc dot gnu.org --- Comment #5 from Robin Dapp --- Did anybody do some further investigation here? Juzhe messaged me that thi= s PR is the original reason for the reversal but I don't yet understand why the register filters don't encompass the full semantics of RVV overlap. I looked into the test case and what happens is that, in order to determine= the validity of the alternatives, riscv_get_v_regno_alignment is first being ca= lled with an M2 mode. Our destination is actually a (subreg:RVVM2SI (reg:RVVM4SI ...) 0), though. I suppose lra/reload check whether a non-subreg destinati= on also works and hands us a (reg:RVVM4SI ...) as operand[0]. We pass this to riscv_get_v_regno_alignment which, for an LMUL4 mode, returns 4, thus wrong= ly enabling the W42 alternatives. A W42 alternative permits hard regs % 4 =3D=3D 2, which causes us to eventu= ally choose vr2 as destination and source. Once the constraints are actually checked we have a mismatch as none of the alternatives work. Now I'm not at all sure how lra/reload use operand[0] here but this can sur= ely be found out. A quick and dirty hack (attached) that checks the insn's destination mode instead of operand[0]'s mode gets rid of the ICE and doesn= 't cause regressions. I suppose we're too far ahead with the reversal already but I'd really have preferred more details. Maybe somebody has had in-depth look but it just wasn't posted yet? --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6034,6 +6034,22 @@ riscv_get_v_regno_alignment (machine_mode mode) return lmul; } +int +riscv_get_dest_alignment (rtx_insn *insn, rtx operand) +{ + const_rtx set =3D 0; + if (GET_CODE (PATTERN (insn)) =3D=3D SET) + { + set =3D PATTERN (insn); + rtx op =3D SET_DEST (set); + return riscv_get_v_regno_alignment (GET_MODE (op)); + } + else + { + return riscv_get_v_regno_alignment (GET_MODE (operand)); + } +} + /* Define ASM_OUTPUT_OPCODE to do anything special before emitting an opcode. */ const char * diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ce1ee6b9c5e..5113daf2ac7 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -550,15 +550,15 @@ (define_attr "group_overlap_valid" "no,yes" (const_string "yes") (and (eq_attr "group_overlap" "W21") - (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[= 0])) !=3D 2")) + (match_test "riscv_get_dest_alignment (insn, operands[0]) != =3D 2")) (const_string "no") (and (eq_attr "group_overlap" "W42") - (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[= 0])) !=3D 4")) + (match_test "riscv_get_dest_alignment (insn, operands[0]) != =3D 4")) (const_string "no") (and (eq_attr "group_overlap" "W84") - (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[= 0])) !=3D 8")) + (match_test "riscv_get_dest_alignment (insn, operands[0]) != =3D 8")) (const_string "no")=