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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/114714] [RISC-V][RVV] ICE: insn does not satisfy its
 constraints (postreload)
Date: Thu, 25 Apr 2024 10:14:41 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114714

--- Comment #7 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:af7d981ba40f145256f6f6d3409451e8fa647f75

commit r14-10118-gaf7d981ba40f145256f6f6d3409451e8fa647f75
Author: Pan Li <pan2.li@intel.com>
Date:   Thu Apr 25 15:04:02 2024 +0800

    RISC-V: Add test cases for insn does not satisfy its constraints [PR114=
714]

    We have one ICE when RVV register overlap is enabled.  We reverted this
    feature as it is in stage 4 and there is no much time to figure a better
    solution for this.  Thus, for now add the related test cases which will
    trigger ICE when register overlap enabled.

    This will gate the RVV register overlap support in GCC-15.

            PR target/114714

    gcc/testsuite/ChangeLog:

            * g++.target/riscv/rvv/base/pr114714-1.C: New test.
            * g++.target/riscv/rvv/base/pr114714-2.C: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>
    Co-Authored-by: Kito Cheng <kito.cheng@sifive.com>=