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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on
 riscv
Date: Tue, 16 Apr 2024 08:43:41 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114733

--- Comment #3 from Richard Biener <rguenth at gcc dot gnu.org> ---
So the issue is that we do

  switch (induction_type)
    {
    case vect_step_op_neg:
      if (TREE_CODE (init_expr) !=3D INTEGER_CST
          && TREE_CODE (init_expr) !=3D REAL_CST)
        {
          /* Check for backend support of NEGATE_EXPR and vec_perm.  */
          if (!directly_supported_p (NEGATE_EXPR, vectype))
            return false;

          /* The encoding has 2 interleaved stepped patterns.  */
          vec_perm_builder sel (nunits, 2, 3);
          machine_mode mode =3D TYPE_MODE (vectype);
          sel.quick_grow (6);
          for (i =3D 0; i < 3; i++)
            {
              sel[i * 2] =3D i;
              sel[i * 2 + 1] =3D i + nunits;
            }

but this scheme doesn't work for a V1DImode vector type.=