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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114734] [11/12/13 regression] RISC-V rv64gcv_zvl256b
 miscompile with -flto -O3 -mrvv-vector-bits=zvl since r8-6047-g65dd1346027bb5
Date: Fri, 03 May 2024 12:52:08 +0000
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X-Bugzilla-Version: 14.0
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114734

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
      Known to work|                            |14.0
            Summary|[11/12/13/14 regression]    |[11/12/13 regression]
                   |RISC-V rv64gcv_zvl256b      |RISC-V rv64gcv_zvl256b
                   |miscompile with -flto -O3   |miscompile with -flto -O3
                   |-mrvv-vector-bits=3Dzvl since |-mrvv-vector-bits=3Dzvl =
since
                   |r8-6047-g65dd1346027bb5     |r8-6047-g65dd1346027bb5

--- Comment #18 from Richard Biener <rguenth at gcc dot gnu.org> ---
We're getting a new RC, so pushed to 14 now as well.=