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From: "rdapp at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114734] [14] RISC-V rv64gcv_zvl256b miscompile with
 -flto -O3 -mrvv-vector-bits=zvl
Date: Tue, 16 Apr 2024 13:14:51 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114734

--- Comment #4 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Ok, it looks like we do 5 iterations with the last one being length-masked =
to
length 2 and then in the "live extraction" phase use "iteration 6".=